This invention concerns a process for accelerated arbitration among several individual processing units, and an arbitration device for a multiprocessor system.
The article on pages 154 to 158 of the journal "Computer Design" for April 1978 describes an arbitration process and device for a multiprocessor system comprising several identical processing units, all connected to the same bus. This is a synchronous arbitrator, which allows rotating priority to be established among the various processing units, so that the bus will not be monopolized by any one of them, and so that processing by the multiprocessor system will be as fast as possible. This arbitrator principally comprises a read-only memory, in which all possible configurations of bus reservation requests and corresponding states are stored.
This existing device requires a large number of connecting wires between the arbitrator and the various processing units, which could prove troublesome when many such units are involved.
Furthermore, the size of the read-only memory used in this arbitrator depends on the number of processing units co-operating with it. If the number of such units is small, read-only storage capacity for the arbitrator is correspondingly low, and the arbitrator is inexpensive and simple to produce; however, if the number of units is high, several large-capacity memories are needed, and the arbitrator becomes complicated and costly.
This invention concerns an arbitration process for several processing units, that allows priorities to be established easily and quickly, even where a large number of units is involved, and also allows determination of priority to be accelerated when only one unit claims priority.
The invention also concerns an arbitration device that overcomes the drawbacks of existing devices, and is simple and inexpensive to produce.